1. Field of the Invention
The present invention relates to a structure of a metal oxide semiconductor transistor (MOS).
2. Description of the Prior Art
As semiconductor components become smaller, transistor manufacturing has been improved significantly in order to manufacture transistors of small volume and high quality. When a salicide (self-aligned silicide) process is performed on a small transistor, the silicon substrates of the source/drain are depleted excessively. This results in the crystal lattices of the source/drain being damaged, and the PN junction between the source/drain and the substrate being too close to the silicide, causing leakage, and the component to lose efficacy.
Therefore, current transistor manufacturing processes utilize a selective epitaxial growth (SEG) process to build a high source/drain of the transistor, so that the silicide is formed without depletion of the silicon substrate, and the efficacy of the component is thereby increased.
Please refer to FIGS. 1 to 5. FIGS. 1 to 5 are schematic diagrams of manufacturing a CMOS transistor according to the prior art. As FIG. 1 shows, a substrate 102 includes an N well 104, a P well 106, and a shallow trench isolation (STI) 108. A plurality of gate structures 110 and 112 are deposited on the substrate 102. The gate structure 110 is formed on the N well 104, the gate structure 112 is formed on the P well 106, and the STI 108 is formed between the adjacent gate structures 110 and 112 in the substrate 102. The substrate 102 is a P type silicon substrate, and the gate structures 110, 112 are made from conductive material such as poly-silicon.
Next, a first light ion implanting process is performed by a mask (not shown), and P type light dopant drains 114 are formed in the N well 104 of the two lateral sides of the gate 110. Afterwards, a second light ion implanting process is performed by another mask (not shown), and N type light dopant drains 116 are formed in the P well 106 of the two lateral sides of the gate 112. The sequence of forming the P type light dopant drain and the N type light dopant drain can be alternated. Subsequently, a dielectric layer (not shown) is deposited on the substrate 102 to cover the gate structures 110 and 112. Next, an anisotropic etch process is performed on the dielectric layer, so as to form a spacer 122 around the gate structures 110, 112.
Please refer to FIG. 2. A patterned photo-resist layer 202 covers the P well 106 and the gate structure 110. Subsequently, the gate structure 110, the spacer 122 around the gate structure 110, and the patterned photo-resist layer 202 form a mask on which a P− ion implanting process is performed, so as to form a P− dopant region 204 outside the spacer 122 and in the N well 104. Next, the patterned photo-resist layer 202 is removed.
Please refer to FIG. 3. A cap layer (not shown) is deposited on the substrate 102. And then, a patterned photo-resist layer 304 is selectively formed on the cap layer and the P well 106. The gate structure 110, the spacer 122 around the gate structure 110, and the patterned photo-resist layer 304 form a mask on which is performed a P+ ion implanting process, so as to form a P+ dopant region 306 outside the spacer 122 and the N well 104. Then, an etching process is performed, and the cap layer becomes the patterned photo-resist layer 304. Next, the patterned photo-resist layer 304 is then removed.
Please refer to FIG. 4. The patterned cap layer 302, the gate structure 110, and the spacer around the gate structure 110 form the mask. An etching process is performed by appropriate etching selectivity and a recess 400 is formed outside between the spacer 122 and the STI 108 and in the N well 104. Next, a SEG process is performed, and an epitaxial silicon layer 402 is formed in each recess 400. The material of the epitaxial silicon layer 402 could be silicon, SiGe, or SiC. Subsequently, the patterned cap layer 302 is removed.
Please refer to FIG. 5. Another patterned photo-resist layer (not shown) is formed on the N well 104. The gate structure 112 and the spacer 122 around the gate structure 112 form the mask. An N+ ion implanting process is performed to form a source/drain 502 outside the spacer 122 around the gate structure 112 and in the P well 106. The source/drain 502 are the N+ dopant regions. Next, the patterned photo-resist layer is removed.
Afterwards, another patterned photo-resist layer (not shown) is formed on the P well 106. The gate structure 110 and the spacer 122 around the gate structure 110 form the mask. A P+ ion implanting process is performed to form the source/drain 504 outside the spacer 122 around the gate structure 110 in the N well 104. The source/drain 504 are P+ dopant regions. Next, the patterned photo-resist layer is removed. Then, an annealing process is performed to activate the dopant in the substrate, and repair the crystal lattice in the surface of the substrate 102, which is damaged by the ion implanting processes. Of course, the sequence of forming the source/drain can be alternated.
At this point, the above-mentioned manufacture is completed. The N channel MOS (NMOS) transistor 506 of the CMOS transistor is formed by the gate structure 112, and the source/drain 502. The P channel MOS (PMOS) transistor 508 of the CMOS transistor is formed by the gate structure 110, and the source/drain 504.
The prior art requires the patterned cap layer 302 to be the hard mask of the recess 400 etching process and the SEG process of the PMOS transistor 508. Forming the patterned cap layer 302 is a necessary process in the prior art. The cap layer, however, which is 300 to 400 angstroms, is deposited on the substrate 102. An etching process is performed on the cap layer to form the patterned cap layer 302. Without the patterned cap layer 302, the etching process on the cap layer cannot be performed completely, and a partial cap layer will remain on the N well 104. The un-etched cap layer on the substrate 102 means the recess 400 etching process cannot form the ideal recess 400, and the transistor cannot have optimum performance. The recess etching process 400 influences the pitch of the poly-line of the gate structure, so the influence on the transistor is huge.